Indiana Δημοσιεύτηκε Ιούλιος 28, 2006 #1 Κοινοποίηση Δημοσιεύτηκε Ιούλιος 28, 2006 Μπήκα σήμερα στο xtreme...και τι να δω...http://www.xtremesystems.org/forums/showthread.php?t=108884και το γιαπωκορεάτικο site με τις πληροφορίες....http://www1.oc.com.tw/forums/msgexcel.asp?id=A03&msgid=214086&n=6&posit=8&more=&remsgid=0¬op=0&allfrom=214071&page=1&itype=1:102::102::102:λέτε να δούμε σύντομα 65Nm από amd? :030: Link to comment Share on other sites More sharing options...
Necro Ιούλιος 28, 2006 #2 Κοινοποίηση Ιούλιος 28, 2006 Viva La Revolution! Link to comment Share on other sites More sharing options...
DennisK Ιούλιος 28, 2006 #3 Κοινοποίηση Ιούλιος 28, 2006 ....123Features for future AMD MicroarchitecturesThese may be present in the original K8L processors or a more future AMD64 chip, by various reports in the time frame of Q1 07, Q2 07, Q3 07, or for socket AM3 chips, Q1 08; (this variation in reports is probably due to reportings about the same microarchitecture core on different platforms, with each source of these reports only given incomplete information); and K10 microarchitecture in years 2008 to 2009.* Four processor cores* independently changeable core voltages* 48-bit memory addressing for the address BUS of massive memory subsystems* official support for coprocessors connected via HyperTransport Expansion Slot (HTX)* Simultaneous DDR2, DDR3 support* FB-DIMM support in server processors (Opterons)* Memory mirroring support and RAS ε????* HyperTransport retry support* New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS* More aggressive prefetching (16 bytes to 32 bytes)* Out of order loads* Double FP units* Z-Ram technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache.* Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for rev. G or rev. H chips.* Large Level-3 non-inclusive cache, initially expected to be a minimum of 2MB shared cache between processing cores on a single die (each with 512 KB of independent second-level cache).* Vector coprocessor support, which will bring 1-2 orders of FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.* Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.* Support for HyperTransport 4.0 at an unspecified date; according to techreport.com[1] and some other sources.* Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Rev. H Opterons.* New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.* Implementation and possibly adding extensions of SSE4 , which AMD codenamed SSE4a.* Possible use of new socket (Socket AM3).* Contain both DDR2 and DDR3 controllers: AM3 chips to be backward compatible with Socket AM2 motherboards; but socket AM2 chips will not be compatible with AM3 motherboards. Link to comment Share on other sites More sharing options...
Zakkorn Ιούλιος 28, 2006 #4 Κοινοποίηση Ιούλιος 28, 2006 * Double FP units Αυτό θέλω να ακούω. :044: Link to comment Share on other sites More sharing options...
DarthMoul Ιούλιος 28, 2006 #5 Κοινοποίηση Ιούλιος 28, 2006 * Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Rev. H Opterons.Εγώ αυτό θέλω. Πότε έρχεται το HT3; Link to comment Share on other sites More sharing options...
WAntilles Ιούλιος 28, 2006 #6 Κοινοποίηση Ιούλιος 28, 2006 Άντε και ξεκινά όπου νά' ναι η τελική κλιμάκωση με την τελική 3η πράξη:RETURN OF THE JEDI Link to comment Share on other sites More sharing options...
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